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as1371 400ma, low input voltage, low quiescent current ldo www.austriamicrosystems.com/ldos/as1371 revision 1.05 1 - 15 datasheet 1 general description the as1371 low input voltage, positive voltage regulator is designed to deliver up to 400ma while consuming typically only 15a of quiescent current. the device operates from input voltages of 1.2v to 3.6v, and is available in fixed output voltages between 0.6v and 3.3v (programmable in 50mv steps). operation at the full 400ma load current is dependent upon the maximum power dissipation available from package and environment. the low input voltage and ultra-low dropout voltage (20mv @ 100ma load and 80mv @ 400ma load) supports single primary cell operation in small applications, when operated with minimum input- to-output voltage differentials. in addition, the regulator provides a power management life extension by operating from pre-existing 1.8v and 2.5v outputs to provide low output voltages for new generation portable processor cores. the device features stable output voltage with ceramic capacitors down to a value of 1f, strict output voltage regulation tolerances (1%), and good line- and load-regulation. the as1371 is available in a 6-pin 2x2 tdfn package and is qualified for -40c to +85c operation. 2 key features ultra-low dropout voltage: 20mv @ 100ma load operating input voltage range: 1.2v to 3.6v output voltages: 0.6v to 3.3v in 50mv steps max. output current: 400ma output voltage accuracy: 1% low shutdown current: 10na low quiescent current: 50a @ max load integrated overtemperature/overcurrent protection under-voltage lockout feature chip enable input power-ok and low battery detection sense input option minimal external components required operating temperature range: -40c to +85c 6-pin 2x2 tdfn package 3 applications the devices are ideal for powering cordless and mobile phones, mp3 players, cd and dvd players, pdas, hand-held computers, digital cameras, and any other hand-held and/or battery-powered device. figure 1. as1371 - typical application diagram input 1.2v to 3.6v c in 1f on off 100k c out 1f output 0.6v to 3.3v in en gnd sense out as1371 pok
www.austriamicrosystems.com/ldos/as1371 revision 1.05 2 - 15 as1371 datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) pin descriptions table 1. pin descriptions pin number pin name description 1 in ldo input . input voltage range: 1.2v to 3.6v. bypass with 1f to gnd. 2 pok power-ok output. active-low, open-drain output indicates an out-of-regulation condition. connect a 100k pull-up resistor to pin out for logic levels. leave this pin unconnected if the power-ok feature is not used. 3 en active-high enable input. a logic low reduces the supply current to < 1a. connect to pin in for normal operation. 4 gnd ground. this pin also functions as a heat sink. solder it to a large pad or to the circuit-board ground plane to maximize power dissipation. 5 sense sense input. represents the input for the power-ok behaviour. if connected to gnd the pok output is related to out. 6 out ldo output. bypass with 1f to gnd. exposed pad gnd exposed pad. this pin also functions as a heat sink. solder it to a large pad or to the circuit- board ground plane to maximize power dissipation. internally it is connected gnd. as1371 1 2 3 in pok en gnd out sense 6 5 4 exposed pad
www.austriamicrosystems.com/ldos/as1371 revision 1.05 3 - 15 as1371 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in section 6 electrical characteristics on page 4 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units notes electrical parameters in and en to gnd -0.3 +5.0 v pok and out to gnd -0.3 v in + 0.3 v input current (latch-up immunity) -100 100 ma norm: jedec 78 electrostatic discharge electrostatic discharge hbm +/- 1000 v norm: mil 883 e method 3015 temperature ranges and storage conditions thermal resistance ja +78.6 oc/w junction temperature +150 oc storage temperature range -55 +125 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 % moisture sensitive level 1 represents a max. floor life time of unlimited
www.austriamicrosystems.com/ldos/as1371 revision 1.05 4 - 15 as1371 datasheet - electrical characteristics 6 electrical characteristics v in = v out (nominal) + 0.5v, en = in, c in = c out = 1f, t amb = -40c to +85oc (unless otherwise specified). typical values are at t amb = +25oc. table 3. electrical characteristics symbol parameter conditions min typ max units t amb operating temperature range -40 +85 c v in input voltage 1.2 3.6 v v out output voltage available in 50mv steps, see ordering information on page 14 0.6 3.3 v output voltage accuracy t amb = +25oc, i out = 1ma, v out > 1v -2 +2 % t amb = -40 to +85oc, i out = 1ma, v out > 1v -3.5 +3.5 i out maximum output current 400 ma i lim current limit 650 ma i q quiescent current i out = 0ma 15 20 a i out = 400ma 50 v in -v out dropout voltage 1 i out = 100ma 20 50 mv i out = 400ma 80 v lnr line regulation i out = 1ma -15 0 +15 mv v ldr load regulation i out = 1ma to 400ma 0.003 %/ma output voltage noise f = 10hz to 100khz, i out = 10ma 100 v rms psrr output voltage ac power-supply rejection ratio f = 10khz, i out = 10ma 50 db shutdown 2 t on exit delay from shutdown 3,4 90 150 s i off enable supply current en = gnd, t amb = +25oc 0.01 1 a en = gnd, t amb = +85oc 0.04 v ih enable input threshold 1.0 v v il 0.4 i en enable input bias current en = in or gnd, t amb = +25oc 0.03 100 na en = in or gnd, t amb = +85oc 0.2 power-ok output v pok power-ok voltage threshold 5 sense = gnd, v pokfalling 90 94 97 % v out sense = gnd, hysteresis 1 v sense power-ok sense voltage threshold v out = 1.05v, v sense falling 650 800 950 mv hysteresis 50 v ol pok output voltage low i sink = 100a 0.4 v
www.austriamicrosystems.com/ldos/as1371 revision 1.05 5 - 15 as1371 datasheet - electrical characteristics note: all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical qual ity control) methods. i pok pok output leakage current 0 v pok 3.6v, t amb = +25oc, v out in regulation 1a thermal protection t shdn thermal shutdown temperature 150 oc t shdn thermal shutdown hysteresis 15 oc 1. dropout voltage = v in - v out when v out is 100mv < v out for v in = v out(nom) +0.5v (applies only to output voltages 1.3v). 2. the rise and fall time of the shutdown signal must not exceed 1ms. 3. the delay time is defined as time required to set v out to 95% of its final nominal value. 4. guaranteed by design. 5. the functionality is proven by production test, limits are guaranteed by design. table 3. electrical characteristics symbol parameter conditions min typ max units
www.austriamicrosystems.com/ldos/as1371 revision 1.05 6 - 15 as1371 datasheet - typical operating characteristics 7 typical operating characteristics v out = 1.8v, v in = 2.3v, i out = 1ma, t amb = +25c (unless otherwise specified). figure 3. output voltage vs. temperature figure 4. line regulation, v out vs. v in ; 1.7 1.725 1.75 1.775 1.8 1.825 1.85 1.875 1.9 -40-200 20406080 temperature (c) output voltage (v) no lo ad iout = 10 ma 1.7 1.725 1.75 1.775 1.8 1.825 1.85 1.875 1.9 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 input voltage (v) output voltage (v) - 40c + 2 5c + 8 5c figure 5. load regulation, v out vs. i out ; figure 6. quiescent current vs. input voltage 1.7 1.725 1.75 1.775 1.8 1.825 1.85 1.875 1.9 0 50 100 150 200 250 300 350 400 output current (m a) output voltage (v) - 40c + 2 5c + 8 5c 0 10 20 30 40 50 60 70 80 90 100 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 input voltage (v) quiescent current (a) no lo ad io ut = 100 ma iout = 400ma figure 7. pok voltage threshold vs. temperature figure 8. dropout voltage vs. output current 90 91 92 93 94 95 96 97 98 99 100 -40-200 20406080 temperature (c) output voltage (% of v outnom ) pok rising pok falling 0 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 300 350 400 output current (m a) dropout voltage (mv) - 40c + 2 5c + 8 5c
www.austriamicrosystems.com/ldos/as1371 revision 1.05 7 - 15 as1371 datasheet - typical operating characteristics figure 9. line transient response; v in = 2.3v to 2.8v, no load figure 10. load transient response; i out = 0ma to 100ma 500mv/div 500mv/div v in v out 100ms/div 500mv/div 50ma/div i out v out 100ms/div figure 11. turn on figure 12. turn off 500mv/div 1v/div e n v out 20s/div 500mv/div 1v/div e n v out 20s/div
www.austriamicrosystems.com/ldos/as1371 revision 1.05 8 - 15 as1371 datasheet - detailed description 8 detailed description the as1371 is a low-dropout, low-quiescent-current linear regulator intended for ldo regulator applications where output curren t load requirements range from no load to 400ma. all devices come with fixed output voltage from 0.6v to 3.3v. (see ordering information on page 14) . the as1371 also features a power-ok output to indicate when the output is within 10% (max) of final value, and also an enable p in. shutdown current for the whole regulator is typically 10na. the device f eatures integrated short-circuit and over current protection. un der-voltage lockout prevents erratic operation when the input voltage is slowly decaying (e.g. in a battery powered application). thermal protectio n shuts down the device when die temperature reaches 150c. this is a useful protection when the device is under sustained short circuit conditi ons. as illustrated in figure 13 , the devices comprise voltage reference, error amplifier, p-channel mosfet pass transistor, power-ok detect logic, internal voltage divider, current limiter, thermal sensor and shutdown logic. the bandgap reference is connected to the inverting input of the error amplifier. the error amplifier compares this reference w ith the feedback voltage and amplifies the difference. if the feedback voltage is lower than the reference voltage, the p-channel mosfet gate is pulled lower, allowing more current to pass to the output, and increases the output voltage. if the feedback voltage is too high, the pass-tr ansistor gate is pulled up, allowing less current to pass to the output. the output voltage feeds back through an internal resistor voltage divi der connected to pin out. figure 13. as1371 - block diagram output voltages standard products are factory-set with output voltages from 0.6v to 3.3v. a two-digit suffix of the part number identifies the nominal output (see ordering information on page 14) . non-standard devices are available. for more information contact: http://www.austriamicrosystems.com/contact en gnd pok out as1371 error amplifie r trimmable reference voltage shutdown/ power-on control logic thermal overload protection bandgap voltage & current reference - + sense power-ok compare logic nmos in
www.austriamicrosystems.com/ldos/as1371 revision 1.05 9 - 15 as1371 datasheet - detailed description power-ok and low-batte ry-detect functionality the as1371?s power-ok or low-battery-detect circuitry is built around an n-channel mosfet. the circuitry monitors the voltage o n pin sense and if the voltage goes out of regulation (e.g. during dropout, cu rrent limit or thermal shutdown) the pin pok goes low. the pi n sense can be connected to a resistive-divider to monitor a particular definable voltage and compare it with an internal voltage reference. i f the sense pin is connected to gnd an internal resistive-divider is activated and connected to the output. therefore, the power-ok functionality can be realised with no additional external components. the power-ok feature is not active during shutdown and provides a power-on-reset function that can operate down to v in = 1.2v. a capacitor to gnd may be added to generate a power-on-reset delay. to obtain a logic-level output, connect a pull-up resistor from pin pok to pin out. larger values for this resistor will help to minimize current consumption; a 100k resistor is perfect for most applications (see figure 1 on page 1) . for the circuit shown in the left of figure 14 on page 11 , the input bias current into sense is very low, permitting large-value resistor-divider net - works while maintaining accuracy. place the resistor-divider network as close to the device as possible. use a defined resistor for r 2 and then calculate r 1 as: where: v sense .... is the internal sense reference voltage. for values see table 3 on page 4 . r 2 .... is the predefined resistor in the resistor divider. in case of the sense pin is connected to gnd, an internal resistor-divider network is activated and compares the output voltage with a 94% (typ.) voltage threshold. for this particular power-ok application, no external resistive components are necessary. current limiting the as1371 include current limiting circuitry to protect against short-circuit conditions. the circuitry monitors and controls the gate voltage of the p-channel mosfet, limiting the output current to 400ma. the p-channel mosfet output can be shorted to ground for an indefinite period of time without damaging the device. thermal-overload protection the devices are protected against thermal runaway conditions by the integrated thermal sensor circuitry. thermal shutdown is an effective instrument to prevent die overheating since the power transistor is the principle heat source in the device. if the junction temperature exceeds 150oc with 15oc hysteresis, the thermal sensor starts the shutdown logic, at which point th e p-channel mosfet is switched off. after the device temperature has dropped by approximately 15oc, the thermal sensor will turn the p-chan nel mosfet on again. note that this will be exhibited as a pulsed output under continuous thermal-overload conditions. note: the absolute maximum junction-temperature of +150oc should not be exceeding during continual operation. (eq 1) r 1 r 2 v in v sense ------------------ 1 ? ?? ?? =
www.austriamicrosystems.com/ldos/as1371 revision 1.05 10 - 15 as1371 datasheet - detailed description operating region and power dissipation maximum power dissipation is determined by the thermal resistance of the case and circuit board, the temperature difference bet ween the die junction and ambient air, and the rate of air flow. the power dissipation of the device is calculated by: maximum power dissipation is calculated by: where: t j - t amb is the temperature difference between the device die junction and the surrounding air. jb is the thermal resistance of the package. ja is the thermal resistance through the circuit board, copper traces, and other materials to the surrounding. note: pin gnd is a multi-function pin providing a connection to the system ground and acting as a heat sink. this pin should be conne cted to the system ground using a large pad or a ground plane. (eq 2) pi out v in v out ? () = (eq 3) p max t j t amb ? jb ja + ------------------------- =
www.austriamicrosystems.com/ldos/as1371 revision 1.05 11 - 15 as1371 datasheet - application information 9 application information capacitor selection an d regulator stability ceramic capacitors are highly recommended as they offer distinct advantages over their tantalum and aluminum electrolytic compo nents. for stable operation with load currents up to 400ma over the entire device temperature range, use a 1f (min) ceramic output capaci tor with an esr <0.2 . use large output capacitor values (e.g. 10f) to reduce noise and improve load transient-response, stability and power-supply rejection. note: some ceramic capacitors exhibit large capacitance and esr variations with variations in temperature. power supply rejection ratio the as1371 is designed to deliver low dropout voltages and low quiescent currents. power-supply rejection is typically 50db at 10khz. to improve power supply-noise rejection and transient response, increase the values of the input and output bypass capacitors, whi ch are shown in figure 14 . the section 6 electrical characteristics on page 4 show also the device line- and load-transient responses. dropout voltage for standard products with output voltage greater than the minimum v in (1.2v), the minimum input-output voltage differential (dropout voltage) determines the lowest usable supply voltage. this determines the useful end-of-life battery voltage in battery-powered systems. the dropout voltage is a function of the p-mosfet drain-to-source on-resistance multiplied by the load current, and is calculated by: where: r ds(on) is the drain-to-source on -resistance. i out is the output current. figure 14. application diagrams (eq 4) v dropout v in v out ? r ds on () i out == input 1.2v to 3.6v c in 1 f on / off c out 1f output 0.6v to 3.3v in en gnd sense out as1371 pok r 2 r 1 input 1.2v to 3.6v c in 1 f on / off c out 1f output 0.6v to 3.3v in en gnd sense out as1371 pok external voltage level detection (input monitoring) internal voltage level detection (output monitoring) r pu 100k r pu 100k
www.austriamicrosystems.com/ldos/as1371 revision 1.05 12 - 15 as1371 datasheet - package drawings and markings 10 package drawin gs and markings figure 15. 6-pin 2x2 tdfn marking package code: xxx - encoded datecode
www.austriamicrosystems.com/ldos/as1371 revision 1.05 13 - 15 as1371 datasheet - package drawings and markings figure 16. 6-pin 2x2 tdfn package diagram
www.austriamicrosystems.com/ldos/as1371 revision 1.05 14 - 15 as1371 datasheet - ordering information 11 ordering information the device is available as the standard products listed in table 4 . note: all products are rohs compliant. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect technical support is found at http://www.austriamicrosystems.com/technical-support for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributor table 4. ordering information ordering code marking output description delivery form package as1371-btdt-105 ao 1.05v 400ma, low input voltage, low quiescent current ldo tape and reel 6-pin 2x2 tdfn as1371-btdt-12 1 1. on request am 1.2v 400ma, low input voltage, low quiescent current ldo tape and reel 6-pin 2x2 tdfn as1371-btdt-15 1 an 1.5v 400ma, low input voltage, low quiescent current ldo tape and reel 6-pin 2x2 tdfn as1371-btdt-18 1 at 1.8v 400ma, low input voltage, low quiescent current ldo tape and reel 6-pin 2x2 tdfn as1371-btdt-20 1 ap 2.0v 400ma, low input voltage, low quiescent current ldo tape and reel 6-pin 2x2 tdfn as1371-btdt-25 1 aq 2.5v 400ma, low input voltage, low quiescent current ldo tape and reel 6-pin 2x2 tdfn AS1371-BTDT-30 1 ar 3.0v 400ma, low input voltage, low quiescent current ldo tape and reel 6-pin 2x2 tdfn as1371-sample 1 as v out 2 2. non-standard devices from 0.6v to 3.3v are available in 50mv steps. 400ma, low input voltage, low quiescent current ldo tape and reel 6-pin 2x2 tdfn
www.austriamicrosystems.com/ldos/as1371 revision 1.05 15 - 15 as1371 datasheet copyrights copyright ? 1997-2010, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the st andard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact

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